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1 of 14 rev: 031704 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, click here: www.maxim-ic.com/errata . general description the ds1216 smartwatch ram and smartwatch rom sockets are 600-mil-wide dip sockets with a built-in cmos watch function, an nv ram controller circuit, and an embedded lithium energy source. the sockets provide an nv ram solution for memory sized from 2k x 8 to 512k x 8 with package sizes from 26 pins to 32 pins. when a socket is mated with a cmos sram, it provides a complete solution to problems associated with memory volatility and uses a common energy source to maintain time and date. the smartwatch rom sockets use the embedded lithium source to maintain the time and date only. a key feature of the smartwatch is that the watch function remains transparent to the ram. the smartwatch monitors v cc for an out-of-tolerance condition. when such a condition occurs, an internal lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent loss of watch and ram data. typical operating circuit features keeps track of hundredths of seconds, seconds, minutes, hours, days, date of the month, months, and years converts standard 2k x 8 up to 512k x 8 cmos static rams into nonvolatile memory embedded lithium energy cell maintains watch information and retains ram data watch function is transparent to ram operation month and year determine the number of days in each month; leap-year compensation valid up to 2100 lithium energy source is electrically disconnected to retain freshness until power is applied for the first time proven gas-tight socket contacts full 10% operating range operating temperature range: 0 c to +70c accuracy better than 1 minute/month at +25 c ordering information part temp range pin-package ds1216b 0c to +70c 28 smartwatch socket ds1216c 0c to +70c 28 smartwatch socket ds1216d 0c to +70c 32 smartwatch socket DS1216E 0c to +70c 28 smartwatch socket ds1216f 0c to +70c 32 smartwatch socket ds1216h 0c to +70c 32 smartwatch socket (see figure 2 for letter suffix marking identification.) selector guide appears on page 2. ds1216 smartwatch ram (ds1216b/c/d/h); smartwatch rom (DS1216E/f) www.maxim-ic.com
ds1216 smartwatch ram/smartwatch rom 2 of 14 pin description rst - reset, active low dq0 - data input/output 0 (ram) a2 - address bit 2 (read/write [rom]) a0 - address bit 0 (data input [rom]) gnd - ground ce - conditioned chip enable, active low oe - output enable, active low we - write enable, active low v cc - switched v cc for 28-/32-pin ram v cc b - switched v cc for 24-pin ram v cc d - switched v cc for 28-pin ram pin configurations selector guide part ram/rom ram density pc board modification required for density upgrade? ds1216b ram 16k/64k no/yes ds1216c ram 64k/256k no ds1216d ram 256k/1m no/yes DS1216E rom 64k/256k no ds1216f rom 64k/256k/1m no ds1216h ram 1m/4m no ds1216b / c / e 28-pin intelligent socket 2 27 w e 4 25 5 24 [a2] 8 21 6 23 9 20 c e 7 22 o e [ a0 ] 10 19 dq0 11 18 12 17 13 16 gnd 14 15 rst 1 28 v cc 3 26 v cc b top view ds1216d/f/h 32-pin intelligent socket [a0] 12 dq0 v cc w e o e c e 1 2 3 4 5 6 7 8 9 [a2] 10 11 13 14 15 16 32 31 29 28 27 26 25 24 23 22 21 20 19 18 17 gnd r st 30 v cc d
ds1216 smartwatch ram/smartwatch rom 3 of 14 detailed description the ds1216 smartwatch ram and smartwatch rom sockets are 600-mil-wide dip sockets with a built-in cmos watch function, an nv ram controller circuit, and an embedde d lithium energy source. the sockets provide an nv ram solution for memory sized from 2k x 8 to 512k x 8 with package sizes from 26 pins to 32 pins. when a socket is mated w ith a cmos sram, it provides a complete solution to problems associated with memory volatility and uses a common energy source to maintain time and date. the smartwatch rom sockets use the embedded lithium source to maintain the time and date only. a key feature of the smartwatch is that the watch function remains transparent to the ram. the smartwatch monitors v cc for an out-of-tolerance condition. when such a condition occurs, an internal lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent loss of watch and ram data. using the smartwatch saves pc board space since the combination of smartwatch and the mated ram take up no more area than the memory alone. the smartwatch uses the v cc , data i/o 0, ce , oe , and we for ram and watch control. all other pins are passed straight through to the socket receptacle. the smartwatch provides timekeeping information in cluding hundredths of seconds, seconds, minutes, hours, days, date, months, and years. the date at th e end of the month is automatically adjusted for months with fewer than 31 days, including correction for leap years. the smartwatch operates in either 24-hour or 12-hour format with an am/pm indicator. operation communication with the smartwatch ram is established by pattern recognition on a serial bit stream of 64 bits that must be matched by executing 64 consecu tive write cycles containing the proper data on dq0. on the smartwatch rom, communication with the clock is established using a2 and a0, and either oe or ce . all accesses that occur prior to recognition of the 64-bit pattern are directed to memory. after the pattern match, the next 64 reads and/or writes are directed to the clock, and the ram is disabled. once the pattern is established, the next 64 read/write cycles will be directed to the rtc registers. when power is cycled, 64 reads should be executed prior to any writes to ensure that the rtc registers are not written. a pattern match is ignored if the rst bit is zero and the rst pin goes low during the match sequence. a pattern match is also terminated if a read occurs during the 64-bit match sequence. pattern match?ram data transfer to and from the timekeeping registers is accomplished with a serial bit stream under control of chip enable ( ce ), output enable ( oe ), and write enable ( we ). initially, a read cycle to any memory location using the ce and oe control of the smartwatch starts the pattern recognition sequence by moving a pointer to the first bit of the 64-bit comp arison register. next, 64 consecutive write cycles are executed using the ce and we control of the smartwatch. these 64 write cycles are used only to gain access to the smartwatch. therefore, any address to the memory in the socket is acceptable. however, the write cycles generated to gain access to the smartwatch are also writing data to a location in the mated ram. the preferred way to manage this require ment is to set aside just one address location in ram as a smartwatch scratch pad. when the first write cycle is executed, it is compared to bit 0 of the 64-bit comparison register. if a match is found, the pointer increments to the next location of the
ds1216 smartwatch ram/smartwatch rom 4 of 14 comparison register and awaits the next write cycle. if a match is not found, the pointer does not advance and all subsequent write cycles are ignored. if a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison regi ster pointer is reset. pa ttern recognition continues for 64 write cycles as described above until all the bits in the comparison register have been matched (this bit pattern is shown in figure 1). with a correct match for 64 bits, the smartwatch is enabled and data transfer to or from the timekeeping registers can pr oceed. the next 64 cycles will cause the smartwatch to either receive or transmit data on dq0, depending on the level of the oe pin or the we pin. cycles to other locations outside the memory block can be interleaved with ce cycles without interrupting the pattern recognition sequence or data tr ansfer sequence to the smartwatch. pattern match?rom communication with the smartwatch is established by pattern recognition of a serial bit stream of 64 bits that must be matched by executing 64 consecutive wr ite cycles, placing address bit a2 low with the proper data on address bit a0. the 64 write cycles are used only to gain access to the smartwatch. prior to executing the first of 64 write cycles, a read cycl e should be executed by holding a2 high. the read cycle will reset the comparison register pointer with in the smartwatch, ensuring the pattern recognition starts with the first bit of the sequence. when the first write cycle is executed, it is compared to bit 0 of the 64-bit comparison register. if a match is found, th e pointer increments to the next location of the comparison register and awaits the next write cycle. if a match is not found, the pointer does not advance and all subsequent write cycles are ignored. if a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison regi ster pointer is reset. pa ttern recognition continues for a total of 64 write cycles as described above, un til all the bits in the comparison register have been matched (this bit pattern is shown in figure 1). with a correct match for 64 bits, the smartwatch is enabled and data transfer to or from the timekeeping registers can proceed. the next 64 cycles will cause the smartwatch to either receive data on data in (a0) or transmit data on data out (dq0), depending on the level of /write read (a2). after power-up, the controller could be in the 64-b it clock register read/write sequence (from an incomplete access prior to power-down). therefore, it is recommended that a 64-bit read be performed upon power-up to prevent accidental writes to the clock, and to prevent reading clock data when access to the ram would otherwise be expected.
ds1216 smartwatch ram/smartwatch rom 5 of 14 figure 1. smartwatch comparison register definition nonvolatile controller operation the ds1216 smartwatch performs circ uit functions required to make a cmos ram nonvolatile. first, a switch is provided to direct power from the battery or v cc supply, depending on which voltage is greater. this switch has a voltage drop of less than 0.2v. the second function that the smartwatch provides is power-fail detection, which occurs at v tp . the ds1216 constantly monitors the v cc supply. when v cc goes out of tolerance, a comparator outputs a power-fa il signal to the chip-enable logic. the third function accomplishes write protection by holding the chip-e nable signal to the memory within 0.2v of v cc or battery. during nominal power-supply conditions, the memory chip-enable signal will track the chip- enable signal sent to the socket with a maximum propagation delay of 7ns for the 5v and 12ns for the 3.3v version. freshness seal each ds1216 is shipped from dalla s semiconductor with its lithium energy source disconnected, ensuring full energy capacity. when v cc is first applied at a level greater than the lithium energy source is enabled for battery-backup operation. 1 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 1 1 0 0 byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 c5 3a a 3 5c c5 3a a 3 5c hex value 7 0 note: the pattern recognition in hex is c5, 3a, 5c, c5, 3a, a3, 5c. the odds of this pattern a ccidentally duplicating and causing inadvertent entry to the smartwatch are less than 1 in 10 19 . this pattern is sent to the smartwatch lsb to msb.
ds1216 smartwatch ram/smartwatch rom 6 of 14 smartwatch register information the smartwatch information is contained in eight registers of 8 bits, each of which is sequentially accessed one bit at a time after the 64-bit pattern recognition sequence has been completed. when updating the smartwatch registers, each must be handled in groups of 8 bits. writing and reading individual bits within a register could produce erroneous results. these read/write registers are defined in figure 3. data contained in the smartwatch registers is in binary-coded decimal (bcd) format. reading and writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of register 0 and ending with bit 7 of register 7. am-pm/12-/24-mode bit 7 of the hours register is defined as the 12-hour or 24-hour mode-select bit. when high, the 12-hour mode is selected. in the 12-hour mode, bit 5 is the am/pm bit with logic high being pm. in the 24-hour mode, bit 5 is the second 10-hour bit (20 to 23 hours). oscillator and reset bits bits 4 and 5 of the day register are used to control the rst and oscillator functions. bit 4 controls the rst (pin 1). when the rst bit is set to logic 1, the rst input pin is ignored. when the rst bit is set to logic 0, a low input on the rst pin will cause the smartwatch to a bort data transfer without changing data in the watch registers. bit 5 controls the oscillator. when set to logic 1, the oscillator is off. when set to logic 0, the oscillator turns on and the watch becomes operational. these bits are shipped from the factory set to logic 1. zero bits registers 1 to 6 contain one or more bits that always read logic 0. when writing these locations, a logic 1 or 0 is acceptable. additional information refer to application note 52: using the dallas phantom real-time clocks (available on our website at www.maxim-ic.com/rtcapps ) for information about using regard ing optional modifications and the phantom clock contained within the smartwatch.
ds1216 smartwatch ram/smartwatch rom 7 of 14 figure 2. reset and memory density options the rst pin on the controller has an intern al pullup resistor. to disable the rst function, the trace between pin 1 on the socket and pin 13 on the controller can be cut. in this case, the socket will ignore the rst input, preventing address transitions from resetting the pattern match, even if the rst bit is enabled. on the ds1216b and ds1216d, the two v cc pins are connected together on the pc board. the switched v cc from the controller is connected to the two v cc pins that connect to the inserted ram. no modifications are required if the lower density ram is used. to use the higher density ram, the trace by the lower density ram v cc pin, identified by a hash mark labeled ?u,? must be cut. the two square- metal pads, labeled ?g,? must be shorted togeth er. this disconnects switched v cc from the pin going to the inserted ram, and connects it to the correspondi ng address input pin for the higher density ram. note: the letter suffix of the smartwatch is located on the pc board.
ds1216 smartwatch ram/smartwatch rom 8 of 14 figure 3. smartwatch register definition 0 0 10 date date 0 0 0 10 month month 0 10 min minutes 0.1 sec 0.01 sec 0 10 sec seconds 12/24 0 10 a/p hr hour 0 0 osc rst 0 day 10 year year 0 1 2 3 4 5 6 7 00-99 00-59 00-59 01-12 01-07 00-23 01-31 01-12 00-99 range (bcd) register 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0
ds1216 smartwatch ram/smartwatch rom 9 of 14 absolute maximum ratings voltage range on any pin relative to ground?????????????????.????-0.3v to +7.0v for 5v operating temperature range?????????????????????????????..?...0c to +70c storage temperature range?????????????????????????????..?...-40c to +70c soldering temperature range??????????????????...?.see j-std-020a specification (note 6) this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time can affect reliability. recommended dc operating conditions (t a = 0c to +70c) parameter symbol min typ max units notes v cc pin, 5v supply v cc 4.5 5.0 5.5 v 1 logic 1 v ih 2.2 v cc + 0.3 v 8 logic 0 v il -0.3 +0.8 v 8 dc electrical characteristics (v cc = 5.0v 10%, t a = 0c to +70c.) parameter symbol min typ max units notes v cc supply i cci 5 ma 1, 2, 3 v cc supply voltage (i cco = 80ma) v cco1(u) v cc - 0.2 v 1, 6 input leakage i il -1.0 +1.0 a 2, 8, 13 output logic 1 voltage (i out = -1.0ma) v oh 2.4 v output logic 1 voltage (i out = -1.0ma) v ol 0.4 v write-protection voltage v tp 4.25 4.5 v backup power characteristics (v cc < v tp ; t a = 0c to +70c.) parameter symbol min typ max units notes ce output v oh(l) v bat - 0.2 v 1 v cc supply voltage (i cco = 10a) v cco2(u) v bat - 0.2 v 1, 6, 14 ram v cc (battery) voltage v bat 2 3 3.6 v 1, 15 recovery at power-up t rec 2 ms v cc slew rate power-down v pf(max) to v pf(min) t f 300 s v cc slew rate power-down v pf(min) to v ba t (min) t fb 10 s ce pulse width t ce 1.5 s 5
ds1216 smartwatch ram/smartwatch rom 10 of 14 capacitance (t a = +25 c) parameter symbol min typ max units notes input capacitance c in 5 pf output capacitance c out 7 pf expected data retention t dr 10 years 14 ac electrical characteristics (v cc = 4.5v to 5.5v, t a = 0c to +70c.) parameter symbol min typ max units notes read cycle time t rc 75 ns ce access time t co 65 ns oe access time t oe 65 ns ce to output low-z t coe 6 ns oe to output low-z t oee 6 ns ce to output high-z t od 30 ns oe to output high-z t odo 30 ns address setup time (rom) t as 20 11 address hold time (rom) t ah 10 12 read recovery t rr 15 ns write cycle time t wc 75 ns write pulse width t wp 75 ns write recovery t wr 15 ns 9 data setup time t ds 35 ns 10 data hold time t dh 0 ns 10 ce pulse width t cw 65 ns rst pulse width t rst 75 ns ce propagation delay t pd 6 ns 7 ce high to power-fail t pf 0 ns
ds1216 smartwatch ram/smartwatch rom 11 of 14 timing diagram: read cycle to smartwatch timing diagram: write cycle to smartwatch
ds1216 smartwatch ram/smartwatch rom 12 of 14 t f t fb v bat (min) v pf (min) v pf (max) t ce t ce t pd v il v il v ih ce (l)* ce (u) v cc (l) *note 1 v bat -0.2v timing diagram: reset for smartwatch timing diagram: power-down timing diagram: power-up
ds1216 smartwatch ram/smartwatch rom 13 of 14 warning: under no circumstances should negativ e undershoots of any amplitude be allowed when the device is in battery-backup mode. water washing for flux remova l will discharge internal lithium source because exposed voltage pins are present. notes: 1) pin locations are designated ?u? when a parameter definition refers to the socket receptacle and ?l? when a parameter definition refers to the socket pin. 2) no memory inserted in the socket. 3) pin 26l can be connected to v cc or left disconnected at the pc board. 4) smartwatch sockets can be successfully proc essed through some conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85 c. however, post-solder cleaning with wate r-washing techniques is not permissible. discharge to the lithium energy source can result, even if deionized water is used. it is equally imperative that ultrasonic vibration is not used in order to avert damage to the quartz crystal resonator employed by the oscillator circuit. 5) t ce max must be met to ensure data integrity on power loss. 6) v cco 1 is the maximum voltage drop from v cc (l) to v cc (u) while vcc(l) is supplying power. v cco 2 is the maximum voltage drop from v bat to v cc (u) while the part is in battery backup. 7) input pulse rise and fall times equal 10ns. 8) applies to pins rst l, a2 l, a0 l, ce l, oe l, and we l. 9) t wr is a functions of the latter occurring edge of we or ce . 10) t dh and t ds are a function of the first occurring edge of we or ce . 11) t as is a function of the first occurring edge of oe or ce . 12) t ah is a function of the latter occurring edge of oe or ce . 13) rst (pin 1) has an internal pullup resistor. 14) expected data retention is base d on using an external sram with a data retention current of less than 0.5 a at +25c. expected data-retention time (time while on battery) for a given ram battery current can be calculated using the following formula: 0.045 / (current in amps) = data-retention time in hours 15) the ds1216 products are shipped with the battery -backup power off. first power-up switches backup battery on to clock and ram v cc pin upon power-down.
ds1216 smartwatch ram/smartwatch rom maxim/dallas semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxim/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2004 maxim integrated products printed usa 14 of 14 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) pkg dim min max min ma x a in. 1.390 1.420 1.580 1.620 mm 35.31 36.07 40.13 41.14 b in. 0.690 0.720 0.690 0.720 mm 17.53 18.29 17.53 18.29 c in. 0.420 0.470 0.400 0.470 mm 10.67 11.94 10.16 11.94 d in. 0.035 0.065 0.035 0.065 mm 0.89 1.65 0.89 1.65 e in. 0.055 0.075 0.055 0.075 mm 1.39 1.90 1.39 1.90 f in. 0.120 0.160 0.120 0.160 mm 3.04 4.06 3.04 4.06 g in. 0.090 0.110 0.090 0.110 mm 2.29 2.79 2.29 2.79 h in. 0.590 0.630 0.590 0.630 mm 14.99 16.00 14.99 16.00 j in. 0.008 0.012 0.008 0.012 mm 0.20 0.30 0.20 0.30 k in. 0.015 0.021 0.015 0.021 mm 0.38 0.53 0.38 0.53 l in. 0.380 0.420 0.380 0.420 mm 9.65 10.67 9.65 10.67 28-pin 32-pin

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